72 lines
1.8 KiB
ArmAsm
72 lines
1.8 KiB
ArmAsm
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#include "cpu/memlayout.h"
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/*
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Memory layout at this point (see https://wiki.osdev.org/Memory_Map_(x86) for more details):
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0x00500 - 0x08fff: usable memory
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0x09000 – 0x14fff: kernel code and global data
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0x15000 - 0x7ffff: usable memory
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0x80000 - 0xfffff: BDA and upper memory
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0x100000 - 0x8000000 (1 MiB - 128 MiB): usable memory
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*/
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.intel_syntax noprefix
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.global _start
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.asciz "kernel start\n"
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_start:
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.code32
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mov dword ptr [patch_addr - KERNBASE], offset gdt32_begin - KERNBASE
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lgdt gdtr32 - KERNBASE
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// zero our PD at 0x1000 and PT at 0x2000
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xor eax, eax
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mov ecx, 2048
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rep stosd
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// Set up the page table for the lowest 4 MiB: PD[0] -> PT
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mov dword ptr [0x1000], 0x2000 | 0x3
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// KERNBASE = 0xF000_0000
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// Use the same page table for the first 4 MiB after KERNBASE: PD[0x3c0] -> PT
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mov dword ptr [0x1000 + (0x3c0 * 4)], 0x2000 | 0x3
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// Identity map the first 2 MiB
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mov edi, 0x2000 // Start of the PT
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mov ebx, 0x00000003 // Present, R/W
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mov ecx, 512 // 2 MiB / 4 KiB = 512
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SetEntry:
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mov dword ptr [edi], ebx
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add ebx, 0x1000
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add edi, 4
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loop SetEntry
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// Load physical address of PD into CR3
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mov edi, 0x1000
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mov cr3, edi
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// Enable paging
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mov eax, cr0
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or eax, 1 << 31 // Set the PG bit
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mov cr0, eax
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.att_syntax
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jmp $0x8, $loadseg - KERNBASE
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.intel_syntax noprefix
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loadseg:
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// jump to the high half
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add esp, KERNBASE
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lea eax, kmain
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jmp eax
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.align 16
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gdtr32:
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.word gdt32_end - gdt32_begin - 1
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patch_addr:
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.long gdt32_begin - KERNBASE
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.align 16
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gdt32_begin:
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.long 0x00000000, 0x00000000 # Null descriptor
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.long 0x0000ffff, 0x00cf9a00 # Code segment
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.long 0x0000ffff, 0x00cf9200 # Data segment
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gdt32_end:
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